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general description the MAX6974/max6975 precision current-sinking, 24-output pwm led drivers drive red, green, and blue leds for full-color graphic message boards and video displays. each output has an individual 12-bit (MAX6974) or 14-bit (max6975) pwm-intensity (hue) control and 7-bit (MAX6974) or 5-bit (max6975) global pwm intensity (luminance) control. the MAX6974/max6975 feature a high-speed, fully buffered cascadable serial interface, open-circuit led fault detection circuitry, as well as a watchdog timer. the driver has three banks of eight outputs, with each bank intended to drive a different color in rgb applica- tions. the full-scale current for each bank of eight out- puts is adjustable from 6ma to 30ma in 256 steps (0.3125% per step) to calibrate each color. the MAX6974/max6975 can optionally multiplex by using outputs mux0 and mux1 , which each drive an external pnp transistor. multiplexing doubles the MAX6974/max6975 drive capability to 48 leds. the MAX6974/max6975 operate from a 3.0v to 3.6v power supply. the led power supply can range from 3v to 7v. the led drivers require only 0.8v headroom above the leds?forward-voltage drop. using a sepa- rate led supply voltage for each led minimizes power consumption. the serial interface uses differential signaling for the high-speed clock and data signals to reduce emi and improve signal integrity. the MAX6974/max6975 buffer all interface signals to simplify cascading devices in modules that use a large number of drivers. an internal watchdog timer, when enabled, automatically clears the pixel-data registers and blanks the display if any of the signal inputs fail to toggle within 40ms. the MAX6974/max6975 are available in 40-pin tqfn packages and operate over the -40? to +125? temperature range. refer to the max6972/max6973 data sheet for a 16-output, 11ma to 55ma software-compatible device. applications led video display panels led message boards variable message signs (vms) signs graphic panels features 24 led current sink outputs (three banks of eight outputs) 48 led drive option when multiplexing 33mhz clock supports up to 63 frames per second of video constant output current calibration from 6ma to 30ma in 256 steps ezcascade interface simplifies multiple driver cascading without external buffers 12-bit or 14-bit individual pwm led intensity controls 7-bit or 5-bit panel pwm-intensity control +3v to +7v led power supply +3.0v to +3.6v logic supply open-circuit led fault detection optional watchdog timer blanks display if interface fails standard -40? to +125? operating temperature range MAX6974/max6975 24-output pwm led drivers for message boards ________________________________________________________________ maxim integrated products 1 19-0555; rev 0; 5/06 for pricing delivery, and ordering information please contact maxim/dallas direct! at 1-888-629-4642, or vis it maxim? website at www.maxim-ic.com. typical operating circuit appears at the end of data sheet. * ep = exposed pad. + denotes lead-free package. MAX6974atl/ max6975atl tqfn-ep top view 35 36 34 33 12 11 13 14 12 + b5 4567 27 28 ep* *ep = exposed paddle. 29 30 26 24 23 22 b4 b3 g2 g1 g0 r7 3 25 37 b2 r6 38 39 40 b1 b0 v dd r5 r4 r3 b6 32 15 g3 b7 31 16 17 18 19 20 g4 8910 21 agnd r2 r1 r0 i.c. loadi din- din+ clki- clki+ mux0 clko+ clk0- dout+ dout- loado v dd g7 g6 g5 mux1 pin configuration ordering information part temp range pin- package pkg code MAX6974 atl+ -40? to +125? 40 tqfn-ep* t4066-3 max6975 atl+ -40? to +125? 40 tqfn-ep* t4066-3 ezcascade is a trademark of maxim integrated products, inc.
MAX6974/max6975 24-output pwm led drivers for message boards 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages with respect to gnd.) v dd ........................................................................-0.3v to +4.0v r0?7, g0?7, b0?7, mux0 , and mux1 ...........-0.3v to +8.0v all other pins..............................................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70?) 40-pin tqfn (derate 37mw/? over +70?) .............2963mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating supply voltage v dd 3.0 3.6 v leds anode voltage (r0?7, g0?7, b0?7, mux0 , and mux1 ) v o 7v f clki = 0hz; clko_, dout_ loaded 200 ; calibration dacs set to 0x01 28 52 f clki = 0hz; clko_, dout_ loaded 200 ; calibration dacs set to 0xff 51 72 supply current i dd f clki = 32mhz; clko_, dout_ loaded 200 ; calibration dacs set to 0xff 54 77 ma input high voltage loadi v ihc 0.7 x v dd v input low voltage loadi v ilc 0.3 x v dd v differential input voltage range clki_, din_ v id ?.15 ?.20 v common-mode input voltage clki_, din_ v cm | v i d / 2| 2.4 v differential input high threshold vdiff th 8 100 mv differential input low threshold vdiff tl -100 -8 mv differential output voltage clko_, dout_ v od termination 200 at receiver _+ and _- inputs ?90 ?50 mv differential output offset clko_, dout_ v os termination 200 at receiver _+ and _- inputs 1.125 1.25 1.375 v input leakage current clki_, din_, loadi i ih , i il -1 +1 ? input capacitance clki_, din_, loadi 10 pf output low voltage loado v olc i sink = 5ma 0.05 0.25 v output high voltage loado v ohc i source = 5ma v dd - 0.5 v dd - 0.2 v electrical characteristics (v dd = 3.0v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v dd = 3.3v, t a = +85?.) (note 1)
MAX6974/max6975 24-output pwm led drivers for message boards _______________________________________________________________________________________ 3 note 1: all parameters tested at t a = +85?. specifications over temperature are guaranteed by design. note 2: specification limits apply to devices at the same t a for t a = t min to t max . note 3: guaranteed by design. parameter symbol conditions min typ max units output slew time loado 20% to 80%, 80% to 20%, load = 10pf 3 ns output low voltage mux_ v olm i sink = 40ma 0.4 v open-circuit detection v ocd 200 mv output voltage slew time r0?7, g0?7, b0?7 80% to 20%, load = 50pf, calibration dacs set to 0xff 100 ns t a = +85? 28 30 32 full-scale port output current r0?7, g0?7, b0?7 i sinkfs v dd = 3.3v, v o = 1.2v, calibration dacs set to 0xff t a = t min to t max 26 34 ma t a = +125? (note 3) ?.7 2.7 t a = +85? ?.7 2 port-to-port current matching r0?7, g0?7, b0?7 i sink v dd = 3.3v, v o = 1.2v, calibration dacs set to 0xff i sink = 30ma (note 2) t a = -40? (note 3) ?.9 3.3 % t a = +85? 0.3 1.15 output load regulation i olr v d d = 3.3v , v o = 1.2v to 3.0v , calibration dacs set to 0x80, i sink = 18ma t a = t min to t max 1.5 ma/v t a = +85? 0.6 1.7 output power-supply rejection i opsr v d d = 3.0 v to 3.6v , v o = 1.2v , calibration dacs set to 0x80, i sink = 18ma t a = t min to t max 2.0 ma/v electrical characteristics (continued) (v dd = 3.0v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v dd = 3.3v, t a = +85?.) (note 1) parameter symbol conditions min typ max units clki_ input frequency f clki 33 mhz clki_ duty cycle 40 60 % clko_ output delay t pd-clko 16 ns din_ setup time t su-din 0.5 ns din_ hold time t hd-din 5ns dout_ output delay t pd-dout 15 ns loado output delay t pd-loado 18 ns loadi hold time t hd-loadi 8ns watchdog period when enabled 40 125 300 ms timing characteristics (v dd = 3.0v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at 3.3v, t a = +85?.) (note 1)
MAX6974/max6975 24-output pwm led drivers for message boards 4 _______________________________________________________________________________________ typical operating characteristics (v dd = 3.3v, t a = +25?, unless otherwise noted.) operating current consumption vs. supply voltage v dd MAX6974 toc01 supply voltage v dd (v) i dd (ma) 3.4 3.3 3.2 3.1 53 49 51 55 45 47 3.0 3.5 3.6 t a = -40 c t a = +25 c t a = +125 c t a = +85 c f clki = 32mhz caldac = 0xff operating current consumption vs. supply voltage v dd MAX6974 toc02 supply voltage v dd (v) i dd (ma) 3.5 3.4 3.3 3.2 3.1 24 26 28 30 20 22 3.0 3.6 t a = -40 c t a = +25 c t a = +85 c t a = +125 c f clki = 0mhz caldac = 0x00 led output sink current vs. output voltage MAX6974 toc03 output voltage (v) i sink (ma) 56 4 3 2 1 5 15 10 25 20 30 35 0 07 t a = -40 c t a = +125 c t a = +25 c t a = +85 c led output sink current vs. output voltage MAX6974 toc04 output voltage (v) i sink (ma) 56 4 3 2 1 5 15 10 25 20 30 35 0 07 v dd = +3.0v v dd = +3.3v v dd = +3.6v
MAX6974/max6975 24-output pwm led drivers for message boards _______________________________________________________________________________________ 5 pin description pin name function 1 mux0 multiplex 0 active-low, open-drain output. use mux0 to drive a pnp transistor. 2 clki+ pwm and serial-interface noninverting clock lvds input 3 clki- pwm and serial-interface inverting clock lvds input 4 din+ serial-interface noninverting data lvds input 5 din- serial-interface inverting data lvds input 6 loadi serial-interface load cmos input 7 i.c. internally connected. connect to gnd. 8?5 r0?7 red led drive outputs. r0 to r7 are open-drain, constant-current sinks. 16?3 g0?7 green led drive outputs. g0?7 are open-drain, constant-current sinks. 24, 40 v dd positive supply voltage. bypass v dd to gnd with a 0.1? ceramic capacitor. 25 loado serial-interface load cmos output 26 dout- serial-interface inverting data lvds output 27 dout+ serial-interface noninverting data lvds output 28 clko- pwm and serial-interface inverting clock lvds output 29 clko+ pwm and serial-interface noninverting clock lvds output 30 mux1 multiplex 1 active-low, open-drain output. use mux1 to drive a pnp transistor. 31 agnd analog ground. connect to gnd. 32?9 b7?0 blue led drive outputs. b0 to b7 are open-drain, constant-current sinks. ep gnd power ground. exposed pad on package underside must be connected to gnd.
MAX6974/max6975 24-output pwm led drivers for message boards 6 _______________________________________________________________________________________ MAX6974 block diagram r led drivers r7?0 i set r7 i set 8-bit g caldac mux1 outputs 7-bit global-intensity pdm modulator 12-bit individual pwm modulator 8 8 288 calibration data latch global- intensity data latch 8 8 mux0 pixel pwm new data latch mux1 pixel pwm new data latch 288 288 ext. pnp ext. pnp 7 7 en en pwm counters sync 288-bit data shift register clki loadi d clko dout din 288 288 288 control mux0 pixel pwm old data latch load 288 288 mux1 pixel pwm old data latch oe load q1 24 7 mux0 output 24-bit new header shift register sync detect r6 r5 r4 r3 r2 r1 r0 8-bit r caldac r led outputs g led drivers g7?0 g7 g6 g5 g4 g3 g2 g1 g0 g led outputs loado i set 8-bit b caldac 8 b led drivers b7?0 b7 b6 b5 b4 b3 b2 b1 b0 b led outputs 8 0/1 oe MAX6974
MAX6974/max6975 24-output pwm led drivers for message boards _______________________________________________________________________________________ 7 max6975 block diagram r led drivers r7?0 i set r7 i set 8-bit g caldac mux1 outputs 5-bit global-intensity pdm modulator 14-bit individual pwm modulator 8 8 336 calibration data latch global- intensity data latch 8 8 mux0 pixel pwm new data latch mux1 pixel pwm new data latch 336 336 ext. pnp ext. pnp 5 5 en en pwm counters sync 336-bit data shift register clki loadi d clko dout din 336 336 336 control mux0 pixel pwm old data latch load 336 336 mux1 pixel pwm old data latch oe load q1 24 5 mux0 output 24-bit new header shift register sync detect r6 r5 r4 r3 r2 r1 r0 8-bit r caldac r led outputs g led drivers g7?0 g7 g6 g5 g4 g3 g2 g1 g0 g led outputs loado i set 8-bit b caldac 8 b led drivers b7?0 b7 b6 b5 b4 b3 b2 b1 b0 b led outputs 8 0/1 oe max6975
MAX6974/max6975 detailed description the MAX6974/max6975 drive 24 nonmultiplexed leds or 48 multiplexed leds for various indoor and outdoor display applications. the ezcascade serial interface enables large multidriver display panels to be con- structed with interconnected MAX6974/max6975 devices (see figure 1). the drivers provide 12-bit (MAX6974) or 14-bit (max6975) individual pwm steps for each led output. four to seven global-intensity bits provide additional pulse-density modulation (pdm) intensity control (see table 1). the MAX6974/max6975 provide 19 bits of total current/intensity control range per color per pixel, or 18 bits if multiplexing. the total pwm dynamic range encompasses gamma correction and, if desired, indi- vidual led calibration. led outputs are grouped in ports (r, g, and b) with eight led outputs per port. each port features its own current calibration control dac (caldac) with 0.31% resolution to set the current. the MAX6974/ max6975 current calibration feature allows unmatched leds from different lots and manufacturers to be color matched. power-up on power-up, the MAX6974/max6975 set the calibration current to the minimum current for all led outputs and clear the global-intensity pdm data, individual-intensity pwm data, and the timing counters. the display remains blank after clki starts running. the watchdog function is inactive after power-up. 24-output pwm led drivers for message boards 8 _______________________________________________________________________________________ host clko dout loado clki din loadi MAX6974/ max6975 1 MAX6974/ max6975 2 MAX6974/ max6975 3 MAX6974/ max6975 n clki din loadi clko dout loado clki din loadi clko dout loado clki din loadi clko dout loado clki din loadi clko dout loado optional feedback figure 1. generic cascaded connection scheme global pdm part led drive outputs led drive current calibration dac range direct multiplexed individual pwm MAX6974 7 bits 6 bits 12 bits 5 bits 4 bits max6975 24 (7v rated) 30ma 6ma to 30ma 3 bits 2 bits 14 bits table 1. comparison of MAX6974/max6975
led-intensity control the MAX6974/max6975 provide three levels of output current control for led drive: calibration dacs (caldacs), global-intensity control, and individual- intensity control. the caldacs set the port output cur- rent levels, while the global-intensity and individual- intensity controls modulate the output current on/off times, providing a fine-resolution control of average output currents (see figure 2). the individual-intensity control operates on each output independently to set each individual led intensity level. the global-intensity controls modulate MAX6974/max6975 outputs simulta- neously for a uniform brightness control without affect- ing color. using a fixed output current level that is modulated only by on/off control leaves the led color unaffected while precisely controlling intensity. finally, all outputs can be turned on and off simultaneously by setting or clearing configuration bit d3 (pwm-on). calibration dacs the 8-bit r, g, and b caldacs set the output current level for all eight outputs in the r, g, and b ports, respectively (see the MAX6974/max6975 block diagrams ). the r caldac, g caldac, and b cal- dac range from a low of 6ma (0x00) to a maximum of 30ma (0xff), providing 94?/step of current trimming. the caldacs are loaded by the serial interface using command 01 (see table 4). the b caldac data is loaded first, followed by the g caldac data, and then the r caldac data (see the serial interface section). the loaded data takes effect immediately. global-intensity control the MAX6974/max6975 adjust global and individual intensities over a time period called a frame. one frame requires 2 19 (524,288) periods of clki and corre- sponds to one video-frame time. video frames generally contain consecutive images displayed rapidly to yield a motion picture display. running the MAX6974/ max6975 at f clki = 31.5mhz allows a video-frame update rate of 60fps for full-motion video (see the MAX6974 video-frame timing and max6975 video- frame timing sections). the MAX6974/max6975 further divide frames into sub- frames to allow a unique combination of global- and individual-intensity controls. the number of subframes is equal to the number of global-intensity control steps. the MAX6974 uses 128 subframes per frame in nonmultiplex ed mode (corresponding to 7-bit global- intensity pdm control) and 64 subframes in multiplexed mode (corresponding to 6-bit global-intensity pdm control). the max6975 features 5-, 4-, 3-, and 2-bit global-intensity control to yield 32, 16, 8, and 4 sub- frames per frame, respectively. the MAX6974/max6975 control global intensity by driving subframes on and off. when a subframe is on, it allows the individual pwm intensity control to be driven on the outputs. subframes that are off do not have any pwm modulation on the outputs. MAX6974/max6975 24-output pwm led drivers for message boards _______________________________________________________________________________________ 9 5 10 15 25 30 (ma) caldac current 20 30ma max 6ma min 127 0 global = 96 global-intensity pdm individual-intensity pwm 4095 0 rn, gn, or bn pwm = 2560 rn, gn, or bn i ave = 10.22ma caldac = 169 255 0 21.8ma 100% 0% 50% 100% 0% 50% 100% 0% 50% figure 2. relationship among the caldacs, global-intensity, and individual-intensity pwm controls
MAX6974/max6975 individual pwm control the MAX6974/max6975 further modulate the time that each subframe is on by a pulse-width modulation (pwm) value. each output current driver in the r, g, and b ports has a unique 12-bit (MAX6974) or 14-bit (max6975) pwm control value providing fine resolution adjustment of average current output. each bit time of the pwm corresponds to one period of clki (t clki ). the pwm setting determines the amount of time, out of the total period, that the output is on. the subframes have pwm off-zones at the start (t spwm ) and end (t epwm ) of the pwm period (see figure 3). the sub- frame period and pwm off zones are shown in table 2 for each device. the MAX6974 subdivides each subframe by 4096 (12-bit) pwm steps and has 16 cycle off zones, leaving an active pwm region of 4064 pwm steps ranging from 16 to 4079. the max6975 subdivides each subframe by 16,384 (14-bit) pwm steps and has 32 cycle off zones, leaving an active pwm region of 16,320 pwm steps ranging from 32 to 16,351. the pwm phase for outputs r0, r2, r4, r6, g0, g2, g4, g6, b0, b2, b4, and b6 use phasing with the outputs on first and off second. inverse phasing is used for outputs r1, r3, r5, r7, g1, g3, g5, g7, b1, b3, b5, and b7 as shown in figure 3 to balance the timing of loads on the led anode power supply. in multiplexed operation, the subframes are shared between mux0 and mux1 active times, effectively reducing the number of subframes by 2. led-intensity control example the three levels of intensity control are shown in figure 2 for one led output driver in a MAX6974 in nonmulti- plexed mode. as an example, the caldac is set to 24-output pwm led drivers for message boards 10 ______________________________________________________________________________________ r0, r2, r4, r6 g0, g2, g4, g6 b0, b2, b4, b6 r1, r3, r5, r7 g1, g3, g5, g7 b1, b3, b5, b7 r0, r2, r4, r6 g0, g2, g4, g6 b0, b2, b4, b6 r1, r3, r5, r7 g1, g3, g5, g7 b1, b3, b5, b7 subframe (n) subframe (n + 1) t spwm t emux t emux mux0 subframe (n), mux0 subframe (n), mux1 mux1 t spwm t spwm t epwm multiplexed nonmultiplexed t spwm t epwm on/off phasing off/on phasing on/off phasing off/on phasing 50% 75% 100% 25% 75% 75% 75% 75% figure 3. multiplexed and nonmultiplexed output driver phasing and example pwm values part subframe (t clki ) t spwm (t clki ) t epwm (t clki ) t emux (t clki ) MAX6974 4096 16 16 16 max6975 16,384 32 32 32 table 2. subframe and pwm timing
169 dec, setting the port output current level to 21.8ma. the global-intensity pdm value is set to 96 dec , producing an even distribution of on subframes out of the 128 possible (shown in figure 4 as subframes 1, 3, 4, 5, etc). each subframe can be on for a pwm duration set by the individual pwm value. the pwm value setting of 2560 dec out of 4096 (12-bit) results in a further reduction of current on time (shown in bold trace). the internal pdm logic spreads the on subframes as evenly as possible among the off subframes to keep the effective scanning frequency high. for applications with a slower clock speed, the max6975 can increase the display refresh rate by a factor of four to eliminate visible flicker. setting configu- ration bit d4 (glb4) to 1 activates the increased refresh rate (see table 6). the increased refresh rate reduces the number of global-intensity settings by a factor of four (see table 3). MAX6974 video-frame timing the MAX6974 supports up to 60 video frames per second (fps). the following equation shows the required clock frequency to support 60 video fps: 60 (video fps) x 4096 (clocks per 12-bit pwm period) x 128 (global-intensity subframes) = 31.5mhz. the MAX6974 supports up to a 33mhz clock signal (~63fps). each 12-bit pwm period contains 4096 clock cycles; multiply that number by 128 (number of global-intensity subframes) to obtain the required number of clock cycles (524,288) per video frame. the MAX6974 requires 36 bits (12 bits per color multiplied by three colors) to drive an rgb pixel. the maximum pixel data that the MAX6974 can send per video frame is 524,288 / 36 or 14,563 pixels, corresponding to 1820 cascaded MAX6974s. max6975 video-frame timing the max6975 also supports up to 60 video frames per second (fps). the following equation shows the required clock frequency to support 60 video fps: 60 (video fps) x 16,384 (clocks per 14-bit pwm period) x 32 (global-intensity subframes) = 31.5mhz. the max6975 supports up to a 33mhz clock signal (~63fps). each 14-bit pwm period contains 16,384 clock cycles; multiply 16,384 by 32 (global-intensity subframes) to obtain the required number of clock cycles (524,288) per video frame. the max6975 requires 42 bits (14 bits per color multiplied by three colors) to drive an rgb pixel. the maximum pixel data that the max6975 can send per video frame is 524,288 / 42 or 12,483 pixels, corresponding to 1560 cascaded max6975s. MAX6974/max6975 24-output pwm led drivers for message boards ______________________________________________________________________________________ 11 169d = 20 subframe number 5 10 15 25 30ma max 6ma min (ma) 01234567891011 caldac current output led current pwm = 2560/4096 one frame is 2 19 (524,288) clki cycles long global pdm = 96/128 subframes on on on on on on on on figure 4. the three levels of led current control (caldac, global-intensity pdm, and individual pwm) modulate the average outpu t current.
MAX6974/max6975 multiplexed vs. nonmultiplexed operation the MAX6974/max6975 can double the number of leds driven from 24 to 48 through multiplexing. when multiplexing, the two outputs, mux0 and mux1 , drive two external pnp transistors, such as fmmtl717, used as common-anode power switches (see figure 5). 24-output pwm led drivers for message boards 12 ______________________________________________________________________________________ r0 r1 r2 r3 r4 r5 r6 r7 (reds) (reds) (greens) (greens) (blues) (blues) q1 fmmtl717 r1 560 r2 180 c1 120pf +5.55v q2 fmmtl717 r1 560 r2 180 c1 120pf g1 g2 g3 g4 g5 g6 g7 g0 b1 b2 b3 b4 b5 b6 b7 b0 mux0 mux1 subframe 15 mux1 16,384 clks subframe 0 mux0 16,384 clks subframe 0 mux1 16,384 clks subframe 1 mux0 16,384 clks subframe 1 mux1 16,384 clks subframe 14 mux0 16,384 clks subframe 14 mux1 16,384 clks subframe 15 mux0 16,384 clks subframe 15 mux1 16,384 clks subframe 0 mux0 16,384 clks one complete 524,288 clock cycle multiplexed video frame figure 5. max6975 multiplexing two sets of eight rgb pixels with a single led supply and subframe timing
setting configuration bit d0 to 1 enables multiplex operation. mux0 and mux1 alternate the led anode drive voltage between two sets of leds. the r, g, and b ports provide individual pwm control during alternate mux cycles as shown in figure 3. the alternating mux cycles reduce the global-intensity resolution (the num- ber of subframes) by half, which reduces the average led current by half. watchdog a selectable watchdog timer monitors serial-interface inputs clki, din, and loadi. enabling the watchdog timer requires that clki, din, and loadi toggle at least once every 40ms. if any of these transitions fails to occur, then the individual-intensity pwm data latches clear. this condition effectively blanks the leds. update the individual-intensity pwm data registers to turn the leds back on. the watchdog timeout does not affect the calibration or global-intensity data, the clock synchronization, or multiplexed/nonmultiplexed setting. use the watchdog functionality in safety-critical appli- cations where a blanked display is safer than an incor- rect display. led open-circuit and overtemperature detection the MAX6974/max6975 feature two fault detection func- tions: open-circuit led outputs and overtemperature. an led open circuit is detected on driver outputs by moni- toring for output voltages below 200mv. when an open circuit is detected, the MAX6974/max6975 increments a fault counter included in the serial-interface protocol that can be routed back to the host transmitter for diag- nostics. any number of open-circuit leds, multiplexed or nonmultiplexed, can be detected, however, only one counter increment occurs per device. the MAX6974/max6975 detect die temperatures above t die = +165? and disable all output drivers by setting all pwm data to zero. the fault counter in the serial-interface protocol is incremented by one count for each cascaded device with an overtemperature condition. the output drivers are turned back on when the die temperature falls below t die = +150?. the fault counter value is distinguished between led open- circuit and ove rtemperature conditions by the serial- interface command used at the time of detection (see the serial interface section for more details). MAX6974/max6975 24-output pwm led drivers for message boards ______________________________________________________________________________________ 13 part mux bit operation pwm res. total clocks per pwm subframe useable clocks per pwm subframe maximum pwm duty cycle 0 nonmultiplex MAX6974 1 multiplex 12 bits 4096 4064 4064 / 4096 = 99.22% 0 nonmultiplex max6975 1 multiplex 14 bits 16,384 16,320 16,320 / 16,384 = 99.61% table 3. MAX6974/max6975 timing comparison part glb4 bit mux bit operation global pdm res. subframes per frame clocks per frame clock frequency (mhz) for 50fps clock frequency (mhz) for 60fps x 0 nonmultiplex 7 bits 128 MAX6974 x 1 multiplex 6 bits 64 524,288 26.2144 31.45728 0 nonmultiplex 5 bits 32 0 1 multiplex 4 bits 16 524,288 26.2144 31.45728 0 nonmultiplex 3 bits 8 max6975 1 1 multiplex 2 bits 4 131,072 6.5536 7.8643
MAX6974/max6975 commands the MAX6974/max6975 have four commands used to load all operating mode and led output current data. each command is uniquely identified by two bits, c1 and c0, embedded in the serial-interface protocol structure. the commands load caldac, load global- intensity pdm, and load configuration each require 24 bits of data (3 bytes) for every cascaded device. the number of bits required for the command load individual pwm varies by device and multiplex mode of operation. each cascaded device can receive unique data for caldacs, global intensity, configuration, and individual pwm output drivers. generally, all cascaded devices are operated in the same configuration mode. the data bytes are transmitted msb first for all commands. the commands are communicated to all cascaded devices by the host using the synchronous serial-interface and protocol structure (see the serial interface section for details). the four commands and the data lengths for each command are shown in table 4. the MAX6974, operating in nonmultiplexed mode, requires twenty-four 12-bit individual pwm data (288 bits total) and requires forty-eight 12-bit data (576 bits total) in multiplexed operation mode. similarly, the max6975, operating in nonmultiplexed mode, requires twenty-four 14-bit individual-intensity pwm data (336 bits total) and requires forty-eight 14-bit (672 bits total) data in multiplexed mode. the individual pwm data are loaded into an intermediate latch and transferred to the actual pwm latches at subframe 0 and pwm clock 0. the r, g, and b calibration dacs are loaded with 8-bit data each in nonmultiplexed and multiplexed modes. data is updated immediately into the caldac latches (see table 8) . the MAX6974/max6975 require one data byte to set the global-intensity pdm for all output drivers. the global- intensity pdm data has a variable number of active bits depending on the multiplex operating mode and, for the max6975, the global-quarter setting. the number of bits used for global-intensi ty control is al ways justified to the lsb of the data byte, as shown in table 5. one byte of data is sent three times with the global-intensity pdm data bits justified to the lsb. data is updated into the pwm latches at subframe 0 and pwm clock 0 (see table 9) . when using the max6975 5-bit global-intensity setting, the settings range from 0 to 63 to set the global intensity from 1 to 64 subframes on to 64 out of 64 subframes on. when using the MAX6974 7-bit global-intensity setting, the settings range from 0 to 127 to set the global inten- sity from 1 out of 128 subframes on to 128 out of 128 subframes on. 24-output pwm led drivers for message boards 14 ______________________________________________________________________________________ cmd[1:0] c1 c0 command data length per cascaded device 288 bits (MAX6974 nonmultiplexed) 576 bits (MAX6974 multiplexed) 336 bits (max6975 nonmultiplexed) 0 0 load individual pwm 672 bits (max6975 multiplexed) 0 1 load caldac 24 bits 1 0 load global-intensity pdm 24 bits 1 1 load configuration 24 bits table 4. commands and data length part glb4 mux total bits msb d7 d6 d5 d4 d3 d2 d1 lsb d0 x 0 7 0 bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] MAX6974 x 1 6 0 0 bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] 0 0 5 0 0 0 bit[4] bit[3] bit[2] bit[1] bit[0] 0 1 4 0 0 0 0 bit[3] bit[2] bit[1] bit[0] 1 0 3 0 0 0 0 0 bit[2] bit[1] bit[0] max6975 1 1 2 0 0 0 0 0 0 bit[1] bit[0] table 5. global-intensity data bit justification
the global-intensity data is received in an intermediate register and is applied to the outputs at subframe 0 and pwm clock 0. the MAX6974/max6975 have one byte of configuration data with 5 active bit settings as shown in table 6. one byte of data containing configuration bit settings is sent three times. data is updated immediately into the cal- dac latches. see table 10 . the loaded configuration settings take effect immediately. serial interface the MAX6974/max6975 feature a fully synchronous and fully buffered serial interface that allows cascading of multiple devices. the serial interface consists of inputs (clki, din, and loadi) and outputs (clko, dout, and loado). the MAX6974/max6975 can pass different data to each cascaded device without any additional inputs to identify the position of the devices in the cascaded chain. MAX6974/max6975 24-output pwm led drivers for message boards ______________________________________________________________________________________ 15 configuration bit acronym function description msb d7 0 not used d6 0 not used d5 0 not used d4 glb4 global quarter enables the reduced global-intensity setting in the max6975 when set to 1. when set, the max6975 uses eight (or four, if multiplexing) pwm subframes. glb4 is set to 0 as power-on default. setting bit d4 has no effect in the MAX6974. d3 pwm-on enable individual pwms turns all individual pwm outputs on when set to 1. power-on default is pwm-on set to 0 to disable all current output drivers. pwm-on can be used to turn all leds on or off without affecting the global-intensity or individual pwm settings. d2 crst reset frame and pwm counters setting crst to 1 synchronously resets internal counters to 0. this action sets the MAX6974/max6975 to subframe 0 of the global-intensity subframe counter and clock 0 of all individual pwm counters. the crst bit is a nonlatching control function that resets to 0 after the counters are set to 0. d1 wdog watchdog enable setting wdog to 1 enables the watchdog timer operation. power-on default is 0. lsb d0 mux multiplex enable setting mux to 1 turns multiplex mode on. power-on default is 0. table 6. load configuration bit definitions
MAX6974/max6975 the serial interface uses the continuously running clock, clki, to synchronously transfer and latch data (33mhz max). the MAX6974/max6975 sample inputs din and loadi on the rising edge of clki and update outputs dout and loado on the rising edge of clki. the MAX6974/max6975 specifications guarantee that cascaded devices observe setup and hold timing from device to device, making external buffers and clock trees unnecessary, even in very large systems. the high-speed clki, clko, din, and dout signals use low-voltage differential signaling (lvds), and the less frequently changing control signals, loadi and loado, use standard cmos. the differential signals are generally referred to in unipolar shorthand; for example, the statement ?lki rising edge?means that clki+ is rising, and clki- is falling. the MAX6974/max6975 use lvds drivers with differential signaling (300mv nominal logic swing around a +1.2v bias) and cascaded cmos control signals to minimize signal-path emi and simplify interface timing and pc board layout. note the differential inputs for the first dri- ver can be driven from +3.3v cmos using lvds level translators, such as the max9112 terminated with 110 (see figure 12). a 25mhz to 33mhz clock frequency is recommended to keep the display refresh rate high. when using the max6975 in reduced global-intensity mode (glb4 = 1 in configuration register), the recommended clock frequency range is 6mhz to 33mhz. serial-interface protocol structure the MAX6974/max6975 serial interface transfers all data and control functions using a protocol structure consisting of header, data, and optional tail segments transmitted in this sequence. the header and tail 24-output pwm led drivers for message boards 16 ______________________________________________________________________________________ t hd-din t hd-loadi clki+ clki- clko+ clko- din+ din- dout+ dout- loadi loado t pd-clko t su-din t pd-dout t pd-loado t su-loadi figure 6. serial-interface timing
segments transfer to all cascaded devices, while the data section reduces in bit length as data transfers through the cascaded devices. when loadi is low, the MAX6974/max6975 continuously monitor din for reception of the sync pattern (see the header segment section). header segment the 24-bit header segment consists of an 8-bit fixed synchronization pattern (sync), a 6-bit command pat- tern ( cmd), and a 10-bit counter (cntr) segment (see table 7). loadi must change from low to high within plus or minus one clock cycle of the first command bit. when the sync bit pattern 0xe8 is recognized, loadi is monitored for the rising edge, allowing the device to internally synchronize loadi to clki. the six command bits, cmd[5:0], consist of bits c1 and c0 repeated three times. the four commands used by the MAX6974/ max6975 are defined by the two bits, c1 and c0. the counter segment is incremented by one for each cascaded device with an internal fault detected. use the counter segment to collect fault data across the cas- caded chain. hdr[23:0] complete 24-bit header segment. sync[7:0] synchronization bit pattern 0xe8 is recognized by the MAX6974/max6975 during intervals when loadi is low. the sync bit pattern, followed by the rising edge of loadi, internally synchronizes the timing relationship between clki and din with the loadi signal. the synchronization pattern must be 0xe8. cmd[5:0] send command bits c1 and c0 three times in succes- sion. the command bits define how many data bits are received and where the data is loaded. the four com- mands are: cntr[9:0] this is the counter for open led or overtemperature fault conditions. the host sends the header segment with the counter value set to zero. the counter value is incre- mented one count by each device that detects a fault condition in the cascaded chain. the accumulated count value returns to the host from the last device in the cas- cade chain. the command determines which fault type is incremented to the counter (see led open-circuit and overtemperature detection counter section): cmd[1:0] = x0 overtemperature faults counted cmd[1:0] = x1 open led faults counted MAX6974/max6975 24-output pwm led drivers for message boards ______________________________________________________________________________________ 17 hdr 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sync cmd cntr 765432101010109876543210 1 1 1 0 1 0 0 0 c1c0c1c0c1c0b9b8b7b6b5b4b3b2b1b0 table 7. serial-interface header c1:c0 command cmd[5:0] 00 load individual pwm 000000 01 load caldac 010101 10 load global-intensity pdm 101010 11 load configuration 111111 header counter clki command 11101000 sync loadi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 din 1 0 (continuous) c1 c0 c1 c0 c1 c0 b9 b8 b7 b6 b5 b4 b3 b2 data b1 b0 figure 7. header-segment timing
MAX6974/max6975 data segment the bit length of the data segment received by the MAX6974/max6975 is dependent on the command specified in the header. the load caldac command has three unique data bytes, while load global-intensity pdm and load configuration each have one byte of data repeated three times. the caldac data within the command load caldac is sent with b caldac data first, fol- lowed by g caldac data, and then r caldac data, as shown in table 8. the data segment of the load individual pwm command has a variable length depending on specific device and configuration settings. the data is always organized as b driver data first in the order of b7 first to b0 last (msb first), followed by the g driver data in the same order of g7 to g0 (msb first), and then the r driver data in the order of r7 to r0 (msb first). tail segment the MAX6974/max6975 allow for an optional string of data bits to be transmitted following all device data bits, which is referred to as the tail segment. the data bits of the tail segment are clocked back to the host, following the header, from the last device in a cascaded chain. the number of bits in the tail segment is optional. the tail carries no device-specific data on din, but provides feedback confirmation to the host that all data bits were extracted by all devices in the cascade chain. 24-output pwm led drivers for message boards 18 ______________________________________________________________________________________ header data 1 data 2 data 3 data n hdr[23:0] b[7:0] g[7:0] r[7:0] b[7:0] g[7:0] r[7:0] b[7:0] g[7:0] r[7:0] b[7:0] g[7:0] r[7:0] table 8. serial format for load caldac header data 1 data 2 data 3 data n hdr[23:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] table 9. serial format for load global-intensity pdm header data 1 data 2 data 3 data n hdr[23:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] d[7:0] table 10. serial format for load configuration header data 1 data 2 data 3 data n hdr[23:0] b7, b6, ?0 b7, b6, ?0 b7, b6, ?0 b7?0 table 11. serial format for load individual pwm (nonmultiplexed) header data 1 data 2 data 3 data n hdr[23:0] b7, b7', b6, b6', ?0' b7, b7', b6, b6', ?0' b7, b7', b6, b6', ?0' b7, b7', b6, b6', ?0' table 12. serial format for load individual pwm (multiplexed) b[7:0] 8-bit data loaded into port b caldac g[7:0] 8-bit data loaded into port g caldac r[7:0] 8-bit data loaded into port r caldac n number of cascaded devices d[7:0] send the 8-bit data for the global-intensity pdm three times (24 total bits) d[7:0] send the 8-bit configuration data three times (24 total bits) b_?_?_ 12-bit (MAX6974) or 14-bit (max6975) data each b_ 12-bit (MAX6974) or 14-bit (max6975) pwm data for each output b_ during multiplex phase mux0 , msb first b_' 12-bit (MAX6974) or 14-bit (max6975) pwm data for each output b_ during multiplex phase mux1 , msb first g_ 12-bit (MAX6974) or 14-bit (max6975) pwm data for each output g_ during multiplex phase mux0 , msb first g_' 12-bit (MAX6974) or 14-bit (max6975) pwm data for each output g_ during multiplex phase mux1 , msb first r_ 12-bit (MAX6974) or 14-bit (max6975) pwm data for each output r_ during multiplex phase mux0 , msb first r_' 12-bit (MAX6974) or 14-bit (max6975) pwm data for each output r_ during multiplex phase mux1 , msb first
serial-interface cascade timing the MAX6974/max6975 serial-interface protocol timing is simplified by the guaranteed setup and hold charac- teristics of the outputs from one device driving the inputs of another. an example of a cascade of three MAX6974/max6975 devices is shown in figure 8. example of serial-interface cascade timing the basic timing of a MAX6974/max6975 cascaded chain of three devices demonstrates the principle that applies to any number of cascaded devices. the first device connected to the host transmitter is referenced as 1, and the remaining devices are referenced as 2 and 3. device 3 outputs connect to the host for commu- nicating diagnostic and fault counter data. the first MAX6974/max6975, device 1, receives the header and captures the first set of data bits. the number of captured bits is determined by the command given in the header. a timing example of the data trans- fer for the load caldac command is shown in figure 9. device 1 does not send the captured data out on dout. instead, device 1 sends out a new header 25 clock cycles after the reception of the first header bit on din. the data flow on each interconnect node is shown in figure 10. after capturing the first data set, device 1 transmits all following data segments and the optional tail segment on dout, delayed by one clki cycle. device 2 receives the new header from device 1, followed by data that now begins with device 2? data set. device 2 repeats the same process as described above; captur- ing the first data set received, appending a new head- er, and passing all subsequent data out dout to the next device 3. device 3 captures the last data set and transmits a header followed by the tail segment. the last header and tail segments are clocked back into the host receiver. the header received by the host contains the updated fault counter data. the tail data bit pattern can be compared to the tail data originally transmitted by the host for data integrity check. MAX6974/max6975 24-output pwm led drivers for message boards ______________________________________________________________________________________ 19 host clko dout loado clki din loadi clk0 d0 load0 clk1 d1 load1 clk2 d2 load2 clk3 d3 load3 MAX6974/max6975 1 MAX6974/max6975 2 MAX6974/max6975 3 clki din loadi clko dout loado clki din loadi clko dout loado clki din loadi clko dout loado figure 8. example showing three-device cascade connection scheme with the interconnecting nodes labeled for clarity data: caldac data 1 (continuous) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 clki loadi din 0 1 b caldac g caldac g caldac b caldac g caldac r caldac data: caldac data 2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 9. timing example showing caldac data set for the first two cascaded devices idle idle idle idle clk0 3 bytes 1 3 bytes 2 3 bytes 3 header 1 t 3 bytes 2 3 bytes 3 header 2 t 3 bytes 3 header 3 t header 4 t 25 clocks 25 clocks 25 clocks d0 d1 d2 d3 figure 10. data cascading example for 24-bit data words
MAX6974/max6975 when the MAX6974/max6975 send individual-intensity pwm data, the data segment bit length is large due to the 12-bit or 14-bit pwm data for each of the 24 outputs (see figure 11). the various data segment bit lengths for each of the four commands and different operating modes is shown in table 4. data capturing is the same as described above with the header segment outputs and data being delayed by the full length of the data bit stream being captured plus one clock cycle. led open-circuit and overtemperature detection counter the MAX6974/max6975 feature led open-circuit detection and overtemperature detection that use the counter section of the header segment to record detected faults. using commands 01 or 11 force the counter to record led open-circuit detection faults. using commands 00 or 10 force the counter to record overtemperature faults. the MAX6974/max6975 detect an open circuit on a driver output by monitoring for output voltages below 200mv. when an open circuit is detected, the MAX6974/ max6975 increment the counter segment data, cntr[9:0], received on din by 1 before transmitting a header and new counter value out dout. regardless of the number of open-circuit outputs on a device, the counter increment is 1. the MAX6974/max6975 detect die temperatures above t die = +165? and disable all output drivers by setting all pwm data to zero. during an overtemperature event, the MAX6974/max6975 increment the counter segment data, cntr[9:0], received on din by 1 before transmitting a header and new counter value out dout. the output drivers are allowed to be on when the die temperature falls below t die = +150?. when there is no fault detected, the counter data is passed directly to dout unaltered. applications information terminations and pc board layout the MAX6974/max6975? layout simplifies cascading multiple devices, as the interface signals flow through from each device. the synchronous and buffered nature of the interface simplifies the board design, but pay attention to signal routing and termination, as with other high-speed logic circuits. terminate the differential input pairs, clki+ and clki-, as well as din+ and din-, with a termination resistor as close as possible to the package. when using the MAX6974/max6975 as the signal source, use a 200 termination resistor. when using a level translator or clock retimer as the signal source, use a 110 termination resistor. route each differential input pair as close parallel tracks with spacing or a gnd trace between the track pair and the next signal track to minimize cross-coupling. track lengths up to a few inches do not require termination-matched tracks (transmission lines). 24-output pwm led drivers for message boards 20 ______________________________________________________________________________________ data 1 pwm 288 bits h1 289 clocks 289 clocks 289 clocks d0 d1 d2 d3 data 2 pwm 288 bits data 3 pwm 288 bits t data 2 pwm 288 bits data 3 pwm 288 bits t h2 data 3 pwm 288 bits t h3 t h4 figure 11. long (288 bits) pwm data cascading shown for MAX6974 in nonmultiplexed mode clki- clko- clko+ clki+ 200 din- dout- dout+ din+ loado loadi n-2 200 MAX6974 clki- clko- clko+ clki+ 110 din- dout- dout+ din+ loado loadi n-1 110 MAX6974 do2- do2+ din2 do1- do1+ din1 max9112 clk din load host n more devices with 200 termination figure 12. typical cascaded serial-interface termination circuit
MAX6974/max6975 24-output pwm led drivers for message boards ______________________________________________________________________________________ 21 use the same length interface signal paths, whether differential or cmos, to ensure a uniform propagation delay for each signal. power-supply considerations the MAX6974/max6975 operate with a power-supply voltage of 3.0v to 3.6v. bypass the v dd power supply to gnd with a 0.1? ceramic capacitor as close as possible to the device pins. if the led supply is shared with the v dd supply, adequately decouple the v dd supply with bulk capacitance to ensure that the fast- rising, high-current led drive currents do not cause transient dips in v dd . driving leds from a supply higher than 7v an external npn transistor in a cascode configuration extends the output drive voltage above 7v. the external pass transistor? emitter clamps to a v be below its base, which is connected to the MAX6974/max6975? supply voltage. an optional emitter resistor reduces the voltage drop across the MAX6974/max6975? output transistor and effectively takes the dissipation off the device into the resistor. the external transistor? collector current is equal to its emitter current (less a small base current), and the MAX6974/max6975 accurately control the emitter current with a constant current sink driver structure. example of using an external npn transistor: v dd = 3.3v ?%, i out = 30ma, external pass transistor v be = 0.7v to 1v at 30ma emitter current. for best output current accuracy, design v o to be at least 1.2v: r1 (max) = (3.15 - 1 - 1.2) / 0.030 = 31.7 , so choose r1 = 30 . MAX6974 max6975 v dd r1 q1 30ma +3.3v +3.3v +24v r1 r2 r3 r4 r5 r6 r7 r0 gnd figure 13. external cascode npn transistor MAX6974 MAX6974 system clk data load clko dino loado clki dini loadi r0/g0/b0 8 rgb leds r1/g1/b1 r2/g2/b2 r3/g3/b3 r4/g4/b4 r5/g5/b5 r6/g6/b6 r7/g7/b7 r0/g0/b0 r1/g1/b1 r2/g2/b2 r3/g3/b3 r4/g4/b4 r5/g5/b5 r6/g6/b6 r7/g7/b7 clko dino loado clki dini loadi typical operating circuit chip information process: bicmos
MAX6974/max6975 24-output pwm led drivers for message boards 22 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps
MAX6974/max6975 24-output pwm led drivers for message boards maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ______________________________ 23 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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